Semiconductor fuse with enhanced post-programming resistance

US8524567B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Andreas Kurz · Oberursel, DE
• Maciej Wiatr · Dresden, DE

Key dates

• Filing date: Sep 13, 2011
• Grant date: Sep 3, 2013
• Expiry date: Dec 2, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.