Vacuum wafer level packaging method for micro electro mechanical system device
US8524571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2011 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Mar 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.