Semiconductor integrated circuit device having a plurality of standard cells for leakage current suppression
US8525552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2012 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Jul 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/922
Abstract
A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.