Family of multiplexer/flip-flops with enhanced testability
US8525565B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2010 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Jun 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.