Resistor thin film MTP memory
US8526214B2 · kind B2 · utility
10Cited by
24References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 15, 2011 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Nov 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.