Semiconductor integrated circuit for low and high voltage operations
US8526221B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2010 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Oct 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1659
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.