Patent · US Active

Method and apparatus for memory test

US8526255B1 · kind B1 · utility

0Cited by

5References

20Claims

0Family size

Assignee

Marvell Israel (M.I.S.L) Ltd. · IL

Inventors

Yosef Solt · Sachnin, IL
Ofir Keren · Safed, IL

Key dates

Filing date	Jun 5, 2012
Grant date	Sep 3, 2013
Priority date	—
Expiry date	Jun 5, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/2602
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a scrambler configured to provide a driving address and associated data to an envelope based on a memory configuration for using a memory array. The driving address and the associated data are used to test the memory array according to a test pattern. The envelope is configured to translate the driving address into a corresponding physical address of the memory array based on the memory configuration.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.