Patent · US Active

Testing of multi-clock domains

US8527824B2 · kind B2 · utility

3Cited by

1References

5Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Swapnil Bahl · New Delhi, IN
Akhil Garg · Sidhauli, IN

Key dates

Filing date	Jan 11, 2013
Grant date	Sep 3, 2013
Priority date	—
Expiry date	Jan 11, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318594
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.