Automated synthesis of high-performance two operand binary parallel prefix adder
US8527920B1 · kind B1 · utility
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Key dates
| Filing date | Jan 29, 2013 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Jan 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for automated synthesis of a parallel prefix device includes determining structural constraints for a given parallel prefix device; generating a plurality of candidate prefix graphs for the parallel prefix device by performing a search of possible prefix graphs meeting the constraints; performing physical synthesis of each of the plurality of candidate prefix graphs to generate performance information for each candidate prefix graph; and determining one or more of the plurality of candidate prefix graphs that meet performance criteria for incorporation into the parallel prefix device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.