System for reducing power consumption of electronic circuit
US8527935B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2013 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Jan 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for reducing power consumption of an electronic circuit design using an EDA tool includes generating a look-up table (LUT) that stores a mapping between a type, a predetermined optimum power input transition time, and at least one characteristic corresponding to each digital logic element present in a cell library of the EDA tool. An input transition time of a first digital logic element is determined. Then, the first logic element is replaced with a second logic element if the input transition time and the predetermined optimum power input transition time of the first logic element are not equal. The second logic element may be replaced with a third logic element if a timing delay of the second logic element is greater than a timing delay of the first logic element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.