Layout design for a high power, GaN-based FET having interdigitated electrodes

US8530903B2 · kind B2 · utility

Assignee

• POWER INTEGRATIONS, INC. · US

Inventors

• Linlin Liu · Fryeburg, US
• Milan Pophristic · New Brunswick, US
• Boris Peres · Jersey City, US

Key dates

• Filing date: Oct 19, 2012
• Grant date: Sep 10, 2013
• Expiry date: Oct 19, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/257

Abstract

A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.