Semiconductor device including a normally-on transistor and a normally-off transistor
US8530904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Feb 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed. One embodiment includes a first semiconductor die having a normally-off transistor. In a second semiconductor die a plurality of transistor cells of a normally-on transistor are formed, wherein one of a source terminal/drain terminal of the normally-on transistor is electrically coupled to a gate terminal of the normally-on transistor and the other one the source terminal/drain terminal of the normally-off transistor is electrically coupled to one of a source terminal/drain terminal of the normally-on transistor. The second semiconductor die includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells. A voltage clamping element is electrically coupled between the gate terminal and the one of the source terminal/drain terminal of the normally-on transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.