Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto
US8530934B2 · kind B2 · utility
2Cited by
66References
15Claims
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Key dates
| Filing date | Oct 11, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Oct 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.