Three-dimensional semiconductor memory device
US8530959B2 · kind B2 · utility
9Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2011 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Dec 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.