Thermally enhanced structure for multi-chip device
US8531032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2011 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Sep 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.