Phase locked loop circuit with selectable feedback paths
US8531222B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2011 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Aug 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit is provided with selectable feedback paths. In one example, a method of operating a device includes passing a clock signal provided by a PLL circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit while at least one external circuit of an external feedback path of the device is disabled during a low power operation mode of the device. The method also includes detecting a lock between the first input signal and a reference signal during the low power operation mode. The lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device. The method also includes passing the clock signal through the external feedback path to provide a second input signal to the PLL circuit. The method also includes switching from detecting a lock between the first input signal and the reference signal to detecting a lock between the second input signal and the reference signal if the external circuit is enabled for the normal operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.