Shift register, scanning signal line drive circuit provided with same, and display device
US8531224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Jul 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver.In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.