Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation
US8531873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2011 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Nov 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The supply node is coupled via a gating device to a supply voltage and ground node is connected to ground. In addition, storage node Q is fed back via feedback loop into a control node of the gating device. In operation, writing into the memory cell may be carried out in a similar manner to dual port SRAM cells, utilizing one or two write circuitries and for writing into storage node Q and storage node QB respectively. Differently from standard SRAM cells, the feedback loop, by controlling the gating device is configured to weaken the write contention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.