Non-volatile semiconductor storage device
US8531891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2012 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Jan 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.