Implementing direct access caches in coherent multiprocessors
US8533401B2 · kind B2 · utility
7Cited by
8References
4Claims
0Family size
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Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Mar 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.