Method for managing branch instructions and a device having branch instruction management capabilities
US8533441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2008 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Jul 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.