Patent · US Active

System for testing connections between chips

US8533543B2 · kind B2 · utility

2Cited by

6References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Jens Barrenscheen · Munich, DE
Harry Siebert · Germering, DE

Key dates

Filing date	Mar 30, 2009
Grant date	Sep 10, 2013
Priority date	—
Expiry date	Sep 21, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/31717
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

In accordance with an aspect of the application, there is provided a system for testing, including a first chip, a second chip, and first and second connections. The first connection is configured to couple a first pin of the first chip to a first pin of the second chip, and to transmit an initial signal from the first chip to the second chip. The second connection is configured to couple a second pin of the first chip to a second pin of the second chip to return the signal as a returned signal to the first chip. The first chip comprises comparison circuitry configured to compare the returned signal with the initial signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.