Reconfigurable scan chain connectivity to enable flexible device I/O utilization
US8533546B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2011 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Dec 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318563
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure provides systems and methods for testing an integrated circuit or device under test (DUT). A DUT of the present invention has a plurality of scan chains, a plurality of shift register elements each associated with a respective one of the scan chains, and a programmable switch matrix to configure shift register elements of a subset of the plurality of shift register elements to cause one shift register element of the subset to receive an interleaved test sequence, and to cause the interleaved test sequence to be shifted to other shift register elements in the subset, and to input deinterleaved test sequences to scan chains associated with the subset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.