Error correcting code logic for processor caches that uses a common set of check bits
US8533572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Jun 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor or other apparatus of an aspect may include a first cache, a first error correction code (ECC) logic for the first cache, a second cache, and a second ECC logic for the second cache. The apparatus may also include an interconnect coupled with or between the first cache and the second cache. The interconnect is operable to transmit data and also check bits corresponding to the data between the first cache and the second cache. A method of an aspect may include accessing data, and check bits corresponding to the data, from a first cache. The data and the check bits may be transmitted over an interconnect from the first cache to a second cache. The data and the check bits may be stored in the second cache. Other methods, apparatus, and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.