Gate array architecture with multiple programmable regions

US8533641B2 · kind B2 · utility

Assignee

• BaySand Inc. · US

Inventors

• Jonathan Park · San Jose, US
• Salah M Werfelli · معلمی نژاد, US
• WeiZhi Kang · Kuala Krai, MY
• Wan Tat Hooi · Kuala Kangsar, MY
• Kok Siong Tee · Bukit Mertajam, MY
• Jeremy Jia Jian Lee · Kuala Kangsar, MY

Key dates

• Filing date: Oct 7, 2011
• Grant date: Sep 10, 2013
• Expiry date: Nov 8, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/988
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.