Inventor · San Jose, CA, US

Jonathan Park

17Patents
5h-index
28Co-inventors
66Inventor score

Filing activity: Dec 29, 1995 → Oct 14, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US6938236B1 Method of creating a mask-programmed logic device from a pre-existing circuit design Physics 22 Expired
US5990502A High density gate array cell architecture with metallization routing tracks having a variable pitch Electricity 20 Expired
US8533641B2 Gate array architecture with multiple programmable regions Electricity 12 Active
US7165230B2 Switch methodology for mask-programmable logic devices Electricity 12 Expired
US9577640B1 Flexible, space-efficient I/O circuitry for integrated circuits Electricity 6 Active
US7689960B2 Programmable via modeling Physics 5 Active
US9811628B1 Metal configurable register file Physics 4 Active
US8773163B1 Flexible, space-efficient I/O circuitry for integrated circuits Electricity 3 Active
US7759971B2 Single via structured IC device Physics 3 Active
US6886143B1 Method and apparatus for providing clock/buffer network in mask-programmable logic device Physics 3 Expired
US7290237B2 Method for programming a mask-programmable logic device and device so programmed Physics 2 Expired
US6742172B2 Mask-programmable logic devices with programmable gate array sites Electricity 2 Expired
US8339844B2 Programmable vias for structured ASICs Electricity 2 Active
US8001509B2 Method for programming a mask-programmable logic device and device so programmed Physics 1 Active
US8788984B2 Gate array architecture with multiple programmable regions Electricity 1 Active
US9590634B1 Metal configurable hybrid memory Electricity 1 Active
US9166593B2 Flexible, space-efficient I/O circuitry for integrated circuits Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.