Nanowire FET and finFET
US8536029B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2012 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jun 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method includes thinning a first region of an active layer, for form a stepped surface in the active layer defined by the first region and a second region of the active layer, depositing an planarizing layer on the active layer that defines a planar surface disposed on the active layer, etching to define nanowires and pads in the first region of the active layer, suspending the nanowires over the BOX layer, etching fins in the second region of the active layer forming a first gate stack that surrounds portion of each of the nanowires, forming a second gate stack covering a portion of the fins, and growing an epitaxial material wherein the epitaxial material defines source and drain regions of the nanowire FET and source and drain regions of the finFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.