Method of forming a topside contact to a backside terminal of a semiconductor device
US8536042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Mar 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.