Method of manufacturing electronic component
US8536048B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jul 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.