Non-volatile memory devices including low-K dielectric gaps in substrates
US8536652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Oct 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.