Chip-last embedded interconnect structures
US8536695B2 · kind B2 · utility
49Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2012 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Apr 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15321
- WIPO fieldPharmaceuticals
- WIPO sectorChemistry
Abstract
The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.