Electronic device packaging structure
US8536701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2012 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Mar 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.