Multi-layer memory system
US8537613B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Feb 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5643
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-later memory and method for operation is disclosed. The memory includes three or more layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer. The method may include the steps of directing host data directly into a first or second layer of the multi-layer memory upon receipt depending on a condition of the data. The method may also include copying data within a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer, as well as transferring data from one layer to the next higher bit per cell layer when layer transfer criteria are met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.