Method of testing bitline in non-volatile memory device
US8537629B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 3, 2012 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jul 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing bitlines in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bitlines crossing the memory cell array. Each of the bitlines has a first end and a second end. The bitlines are divided into a first group and a second group. The testing method includes applying a supply voltage (for charging) or a ground voltage (for discharging) to a specific group of bitlines. The bitlines are tested in two testing stages, namely an open-circuit bitline test and a short-circuit bitline test, based on the feature that a defective bitline cannot be charged or discharged. The open-circuit bitline test and the short-circuit bitline test are quick and dispense with a lengthy programmed/erasing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.