Reassembly of mini-packets in a buffer
US8537859B2 · kind B2 · utility
2Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | May 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/34
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system comprises a processor, a reassembly buffer that receives mini-packets, and at least one data structure that comprises bits. The bits indicate the presence or absence of each of the mini-packets in the reassembly buffer and further indicate whether one of the mini-packets is a final mini-packet in a series of the mini-packets. The processor uses the bits to determine whether all mini-packets forming the series are present in the reassembly buffer. As a result of the determination, the processor causes the series to be read from the reassembly buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.