Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operation
US8539209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2009 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jul 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor breakpoint-checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.