System yield optimization using the results of integrated circuit chip performance path testing
US8539429B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2012 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Aug 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value). Optionally, simulation of such processing can be performed during design of the IC chip for incorporation into the system in order establish the initial chip dispositioning rule in the first place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.