Multilayer barrier III-nitride transistor for high voltage electronics
US8541817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2010 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Mar 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
An improved high breakdown voltage semiconductor device and method for manufacturing is provided. The device has a substrate and a AlaGa1-aN layer on the substrate wherein 0.1≦a≦1.00. A GaN layer is on the AlaGa1-aN layer. An In1-bGabN/GaN channel layer is on the GaN layer wherein 0.1≦b≦1.00. A AlcIndGa1-c-dN spacer layer is on the In1-bGabN/GaN layer wherein 0.1≦c≦1.00 and 0.0≦d≦0.99. A AleIn1-eN nested superlattice barrier layer is on the AlcIndGa1-c-dN spacer layer wherein 0.10≦e≦0.99. A AlfIngGa1-f-gN leakage suppression layer is on the AleIn1-eN barrier layer wherein 0.1≦f≦0.99 and 0.1≦g≦0.99 wherein the leakage suppression layer decreases leakage current and increases breakdown voltage during high voltage operation. A superstructure, preferably with metallic electrodes, is on the AlfIngGa1-f-gN leakage suppression layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.