Three-dimensional (3D) stacked integrated circuit testing
US8542030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2010 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Mar 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/287
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.