Apparatus including memory channel control circuit and related methods for relaying commands to logical units
US8543758B2 · kind B2 · utility
16Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 31, 2011 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Oct 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.