Method and apparatus for serial scan test data delivery
US8543876B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 2010 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Jun 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A design for test (DFT) circuitry which delivers serial data serially is disclosed. The DFT circuit has a transceiver to receive serial data and then deserialize the serial data into deserialize data. The DFT circuit also has a control logic block which receives the deserialize data and stimulates at least one test element with the test data. The test element will generate an output response from the stimulus. The DFT circuit also has an output response block which receives the output from the test element and analyses the output response. Utilizing this DFT circuitry, a high speed data delivery method can be used for testing a device-under-test (DUT). Such method could reduce test time and the test cost associated with test process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.