Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
US8543954B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2008 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Apr 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.