Constraint optimization of sub-net level routing in asic design
US8543964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2011 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Oct 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.