Test path selection and test program generation for performance testing integrated circuit chips

US8543966B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jeanne P. Bickford · South Burlington, US
• Peter A. Habitz · South Burlington, US
• Vikram Iyengar · South Burlington, US
• David E. Lackey · Jericho, US
• Jinjun Xiong · Yorktown Heights, US

Key dates

• Filing date: Nov 11, 2011
• Grant date: Sep 24, 2013
• Expiry date: Nov 11, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318541
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.