Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8546250B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Aug 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.