Three-dimensional (3D) integrated circuit with enhanced copper-to-copper bonding
US8546956B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1306
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.