Area-efficient data line layouts to suppress the degradation of electrical characteristics
US8547766B2 · kind B2 · utility
1Cited by
2References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 24, 2010 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | May 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.