Receiver with clock recovery circuit and adaptive sample and equalizer timing
US8548110B2 · kind B2 · utility
17Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2007 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Jun 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.