Interrupt source controller with scalable state structures
US8549202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2010 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Oct 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor core, a system memory, coupled to the processor core, that includes an interrupt data structure including a plurality of entries each associated with a respective one of a plurality of interrupts. An input/output (I/O) subsystem including at least one I/O host bridge and a plurality of partitionable endpoints (PEs) each having an associated PE number. The I/O host bridge, responsive to receiving a message signaled interrupt (MSI) including at least a message address, determines from the message address a system memory address of a particular entry among the plurality of entries in the interrupt data structure, accesses the particular entry, and, based upon contents of the particular entry, validates authorization of an interrupt source to issue the MSI and presents an interrupt associated with the particular entry for service.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.