Multiprocessor system and operating method of multiprocessor system
US8549227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2008 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Nov 2, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one aspect of embodiments, a multiprocessor system includes a cache memory corresponding to each of the processors, a hierarchy setting register in which the hierarchical level of each cache memory is set, an access control unit that controls access between each cache memory. The hierarchical level of the cache memory for each processor is stored in a rewritable hierarchy setting register. Each processor handles a cache memory corresponding to another processor as the cache memory having a deeper hierarchy than the cache memory corresponding to the each processor. As the result, each processor can access all the cache memories, and therefore the efficiency of cache memory utilization can be improved and the hierarchical level can be set so that the latency becomes optimal for each application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.